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IP1718 LF
Preliminary Data Sheet
18-port 10/100Mbps Smart Switch Controller
Features
Embeds 1.5 Mb packet buffer Handles up to 4K MAC address entries Supports non-blocking wire speed operation Provides 16-port SS-SMII and 2-port MII Supports 2 ports selectable normal MII, reverse MII All I/O signals can operate at 3.3V or 1.8V. Supports up to 18 port based VLAN group Supports 256 levels of data rate control Captures BPDU, IGMP and OSPF ...packet and forward to the CPU port. Suppress/enable per port address learning. Embeds two levels of priority queues for VLAN tag, physical port and IP Differentiated Service. Supports flexible port trunking configuration: up to 3 groups and up to 4 ports for each group Embeds an internal regulator controller to simplify the system design. Power supply: 1.8V for core logic; optional 3.3V or 1.8V for I/O. 128 pin QFP package Adjustable I/O driving capability Support packet length up to 1536 Bytes Spanning Tree state support. Supports 3 kinds of port mirrioring methods HOL blocking prevention Only one 25MHz crystal needed Broadcast storm control support Programmable MAC address table through 2 serial pins. Support Lead Free package (Please refer to the Order Information)
General Description
Supporting 16-port SS-SMII, 2-port MII and various advanced features, the IP1718 LF fits both the office switch and the ETTH( Ethernet to the Home) application. The IP1718 LF embeds internal SSRAM for the use of the packet buffer and the MAC address table. Besides the traditional switch functions, the IP1718 LF provides the easy-to-design solution, fitting the requirement of most switch application. The IP1718 LF also supports some features which can simplify the customer's design from the viewpoint of the system. The embedded regulator controller can reduce the component number on the system board. The web management can be easily accomplished by adding an external CPU with protocol stack. All the I/O pins can operate at 3.3V or 1.8V, providing more design flexibility for power supply distribution. The IP1718 LF embeds 1.5Mb internal packet buffer and stores up to 4K MAC address entries, making it suitable for the generic switch application. In addition, the IP1718 LF supports a wide range of data rate for both egress and ingress, which is useful in the ETTH(Ethernet to the Home) application. The higher layer data packet such as BPDU, IGMP, OSPF can be forwarded to either the 17th or 18th (CPU) port. The flexible trunk configuration allows the user to scale the switch interconnection bandwidth. When the port mirroring function is enabled, the data traffic on the source port will be forwarded to a specified destination port, making the switch administration easier. Supporting up to 18 port based VLAN groups, the IP1718 LF can be configured to fit various traffic partitions. The CoS function is accomplished by configuring the priority of the physical port, the 802.1Q VLAN tag and IP DSCP(Differentiated Service Code Point). In order to fit the application of some special environment, the address learning and the MAC address table aging can be disabled.
1/33 Copyright (c) 2003, IC Plus Corp.
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Table Of Contents
Features .................................................................................................................................................................. 1 General Description................................................................................................................................................. 1 Table Of Contents.................................................................................................................................................... 2 Revision History....................................................................................................................................................... 3 1 Pin Diagram...................................................................................................................................................... 4 2 Block Diagram .................................................................................................................................................. 5 3 Pin description.................................................................................................................................................. 6 Pin description (continued)...................................................................................................................................... 7 Pin description (continued)...................................................................................................................................... 9 Pin description (continued).................................................................................................................................... 10 4 Functional Description.................................................................................................................................... 11 4.1 Medium Access Control(MAC)........................................................................................................... 11 4.1.1 Data Rate Control ................................................................................................................. 11 4.1.2 Flow Control.......................................................................................................................... 11 4.2 Switch Engine and Queue Management ........................................................................................... 12 4.2.1 Store & Forward Mechanism ................................................................................................ 12 4.2.2 Address Learning and aging time ......................................................................................... 12 4.2.3 Class of Service .................................................................................................................... 12 4.2.4 Port_based VLAN ................................................................................................................. 13 4.2.5 Trunk Channel ...................................................................................................................... 14 4.2.6 Port Mirroring ........................................................................................................................ 14 4.2.7 Queue Management ............................................................................................................. 14 4.2.8 Broadcast Storm Control....................................................................................................... 15 4.2.9 Handling the Higher Layer Protocol...................................................................................... 15 4.2.10 Port Security ......................................................................................................................... 15 5 System Operation .......................................................................................................................................... 16 5.1 Reset and EEPROM Download Procedure ....................................................................................... 16 5.2 Polling/Writing the PHY...................................................................................................................... 16 5.3 Programming the Internal Registers .................................................................................................. 17 5.4 SS-SMII.............................................................................................................................................. 17 6 Register Map .................................................................................................................................................. 19 7 Electrical Characteristics................................................................................................................................ 28 7.1 Absolute Maximum Rating................................................................................................................. 28 7.2 AC Characteristics ............................................................................................................................. 28 7.3 DC Characteristics ............................................................................................................................. 31 8 Order Information ........................................................................................................................................... 32 9 Package Detail ............................................................................................................................................... 33
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Revision History
Revision # Change Description IP1718 LF-DS-R01 Initial release. IP1718 LF-DS-R02 Functions for pin 117 & pin 119 are re-defined. The register 2 description is revised. Revise the timing chart of SCPUIO and the SCPUC. IP1718 LF-DS-R03 Revised the pin diagram. Revise the pin description of pin 50, pin 53, pin 107 ~ pin 112. Add pin description of the pin 97. IP1718 LF-DS-R04 Revise the pin diagram. Revise the pin description for pin 89, pin 90, pin 105 and pin 106. IP1718 LF-DS-R05 Add the order information for lead free package. Update page 25, (6DH)
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January 27, 2005 IP1718 LF-DS-R05
1
Pin Diagram
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 M2RXD2 M2RXD3 M3RXC M2TXC M2TXD0/Port5_Pri_ON M2TXD1/Port6_Pri_ON M2TXD2/WRR_Ration_Set0 M2TXD3/WRR_Ration_Set1 M2TXEN M2COL GND VDD18 VDD33 GND P1TXD/1st MII_Force_Link P1RXD P2TXD/2nd MII_Force_Link P2RXD P3TXD/IO_Slew_F P3RXD P4TXD/IO_Drive0 P4RXD RXSYNC1 TXSYNC1 TXCLK1 P5TXD/IO_Drive1
Copyright (c) 2003, IC Plus Corp.
IP1718 LF
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 GND VDD33 GND VDD18 RXCLK1 P5RXD P6TXD/MII 1_Link_CPU P6RXD P7TXD/MII 2 Link CPU P7RXD P8TXD/MII 1_Rev_MII P8RXD MDC MDIO P9TXD/MII 2_Rev_MII P9RXD P10TXD/Test_Mode0 P10RXD P11TXD/Test_Mode1 P11RXD P12TXD P12RXD VDD33 GND RXSYNC2 TXSYNC2 TXCLK2 P13TXD/F_Ctrl_OFF RXCLK2 P13RXD P14TXD/BKP_OFF P14RXD P15TXD/BCST_Ctrl_ON P15RXD P16TXD/A P16RXD VDD18 GND GND Fast_Test_ON GND IP_Pri_ON GND TAG_Pri_ON GND VDD18 GND GND PBDU_Bcast_OFF N.C VDD33 GND N.C GND GND Trunk0_ON1 GND Trunk0_ON0 GND Home_VLAN_ON GND Aging_OFF GND VDD33
GND 102 VDD33 101 M2RXD1 100 M2RXD0 99 M2RXDV 98 97 CLK25M 96 M1COL M1TXEN 95 Port4 Pri ON/M1TXD3 94 Port3_Pri_ON/M1TXD2 93 Port2_Pri_ON/M1TXD1 92 Port1_Pri_ON/M1TXD0 91 90 M1TXC M1RXC 89 M1RXD3 88 M1RXD2 87 M1RXD1 86 M1RXD0 85 M1RXDV 84 VDD33 83 GND 82 GND 81 VDD18 80 CPU_DA 79 CPU_CL 78 INT 77 EEDAT 76 EECLK 75 SCAN_MODE 74 IO_PWR 73 RESET 72 X2 71 X1 70 GND 69 VDDPLL 68 REG18 67 VDD33 66 GND 65
IP1718 LF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
Preliminary Data Sheet
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
2 Block Diagram
PLL/ Clock generator Regulator
PHY Control I/F
Frame Buffer
EEPROM Register
Memory controller/ BIST
Tx/Rx FIFO/DMA CPU Interface
MAC Address Table
Address Resolution Engine
10/100M MAC
...
10/100M MAC
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
3 Pin description
Description Positive power or ground I: Input pin; O:Output pin Input latched upon reset Label P1TXD, P2TXD, P3TXD, P4TXD, P5TXD, P6TXD, P7TXD, P8TXD, P9TXD, P10TXD, P11TXD, P12TXD, P13TXD, P14TXD, P15TXD, P16TXD, TXSYNC1, TXSYNC2, TXCLK1, TXCLK2, P1RXD, P2RXD, P3RXD, P4RXD, P5RXD, P6RXD, P7RXD, P8RXD, P9RXD, P10RXD, P11RXD, P12RXD, P13RXD, P14RXD, P15RXD, P16RXD, GND Type Type PD, PU I/O Description PD:Pulled down with internal resistor PU:Pulled up with internal resistor Bi-direction Input/Output Description SS-SMII transmit data output for port 1 to port 16.
Type P I; O IL
Pin No. SS-SMII 117, 119 121, 123, 128, 7, 9, 11, 15, 17, 19, 21, 28, 31, 33, 35, 126, 26, 127, 27, 118, 120, 122, 124, 6, 8, 10, 12, 16, 18, 20, 22, 30, 32, 34, 36, 42, 44, 46, 48, 56, 60, 62, 64 49, 55 125, 25, 5, 29,
O
O O I
SS-SMII synchronization output for transmit data SS-SMII transmit clock output SS-SMII receive data input
I
Should be tied to GND.
RXSYNC1, RXSYNC2, RXCLK1, RXCLK2,
I
SS-SMII receive synchronization input
I
SS-SMII receive clock input
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Pin description (continued) Pin No. Label Type O O I I I/O I/O O O I I I/O I/O I/O O I/O Description 1st MII (port 17) transmit enable 1st MII (port 17) transmit data output 1st MII (port 17) receive valid 1st MII (port 17) receive data input 1st MII (port 17) transmit clock. Input for normal (MAC mode) MII. Output for reverse (PHY mode) MII 1st MII (port 17) receive clock. Input for normal (MAC mode) MII. Output for reverse (PHY mode) MII. 2nd MII (port 18) transmit enable 2nd MII (port 18) transmit data output 2nd MII (port 18) receive valid 2nd MII (port 18) receive data input 2nd MII (port 18) transmit clock. Input for normal (MAC mode) MII. Output for reverse (PHY mode) MII 2nd MII (port 18) receive clock. Input for normal (MAC mode) MII. Output for reverse (PHY mode) MII. 2nd MII (port 18) collision input. Input for normal MII Output for reverse MII Clock for serial management bus. It's recommended to add a 30pf capacitor to ground for noise filetrring. I/O data for serial manment bus. It's recommended to add a 4.7K pull up resistor connecting to VDD and a 30pf capacitor connecting to ground. Crystal/ Oscillator 25MHz input Crystal output System reset (low active). Should be kept at "low" for at least 10 microseconds. This output pin is 25MHz clock signal which is the counterpart of the clock generated by the X'tal placed on X1 & X2.
MII/Reverse MII 95 M1TXEN 94, 93, 92, 91 84 88, 87, 86, 85 90 89 111 110,109,108,1 07 98 M1TXD[3:0] M1RXDV M1RXD[3:0] M1TXC M1RXC M2TXEN M2TXD[3:0] M2RXDV
104,103,100,9 M2RXD[3:0] 9 106 105 112 13 14 M2TXC M2RXC M2COL MDC MDIO
Miscellaneous 70 X1/OSCI 71 72 97 X2 RESETB CLK25M
I O I O
75 76 78
SCL SDA SCPUC
O, PU Serial EEPROM clock output I/O,PU Serial EEPROM data I, PU Serial CPU access clock input. Please see the section of "Programming the Internal Register" for the usage of SCPUC and SCPUIO. Serial CPU data
79 77 74
SCPUIO INTB TEST
I/O, PU
O, PU Interrupt output. Active low. O, PD Test mode control.
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Copyright (c) 2003, IC Plus Corp.
IP1718 LF
Preliminary Data Sheet
73 67 50, 53 IO_PWR REG18 N.C I O Power selection for I/O pad. 0:1.8V; 1:3.3V. 1.8V regulator control. This pin can be connected to the base of the PNP transistor to generate the 1.8V power. Reserved for IC test. Leave it unconnected in application.
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Pin description (continued)
Pin No. Label Type P P P P P P 1.8V Power for PLL Ground for PLL 1.8V Power for Core circuit Ground for core circuit 3.3/1.8V Power for I/O PAD Ground for I/O PAD Description Power & Ground 68 VDDPLL 69 4,37,57,80,114 GNDPLL VDD18
3,38,58,81,113 GND18 2,23,39,52,66,8 VDD33 3,101,115 1,24,40,51,65,8 GND33 2,102,116
Power On setting. These pins' state will be latched upon reset 117 1st MII_Force_Link IL, PU This pin is pulled up internally. Connecting a pull down resistor to this pin will force the 1st MII linking to the external device regardless of the PHY polling status, 119 2nd MII_Force_Link IL, PU This pin is pulled up internally. Connecting a pull down resistor to this pin will force the 2nd MII linking to the external device regardless of the PHY polling status, IL, PD Output PAD slew rate setting. 1: fast, 0: normal (Default) IL, PD Output PAD driving current capability 00 : 4mA (Default) 01 : 8mA 10 : 12mA 11 : 16mA IL, PD 1st MII (port 17) linked to CPU. 1: 1st MII is connected to CPU. 0: 1st MII is the normal port (Default) IL, PD 2nd MII (port 18) linked to CPU. 1: 2nd MII is connected to CPU. 0: 2nd MII is the normal port (Default) IL, PD 1st MII (port 17) is reverse MII interface 1: Reverse MII; 0:Normal MII (Default). IL, PD 2nd MII (port 18) is reverse MII interface. 1: Reverse MII; 0:Normal MII (Default). IL, PD Reserved for IC test. IL, PD Transmit IPG compensation (+80ppm) 1: Enable; 0: Disable (Default) IL, PD Disable the full duplex flow control of all ports 1: Disable; 0: Enable (Default) IL, PD Disable the half duplex backpressure control of all ports. 1: Disable; 0: Enable (Default). IL, PD Enable the broadcast storm control 1: Enable; 0: Disable (Default) IL, PD 1: Auto turn off the flow control, when the flow control and the priority is enabled. 0: Flow control works normally (Default)
9/33 Copyright (c) 2003, IC Plus Corp. January 27, 2005 IP1718 LF-DS-R05
121 128, 123
IO_SLEW IO_DRIVE[1:0]
7
MII 1_LINK_CPU
9
MII 2_LINK_CPU
11 15 19,17 21 28 31 33 35
MII 1_REV_MII MII 2_REV_MII TEST_MODE[1:0] IPG_COMP_EN FCTRL_OFF BKP_OFF BCST_CTRL_EN AUTO_OFF_FC
IP1718 LF
Preliminary Data Sheet
Pin description (continued)
Pin No. Label Type Description Power On setting. These pins will be latched upon reset (continued) 41 43 AGING_OFF HOME_VLAN_EN IL, PD Disable the MAC address table aging function 1: Disable; 0: Enable (Default) IL, PD 1: Enable the home VLAN setting : Port 1 ~ Port16 are all individual VLAN shared with 2 MII ports. For example, Port 1, port 17 and port 18 form a VLAN group, etc. 1: Enable; 0: Disable (Default) IL, PD The trunk group 0 setting: 00 : no trunk (Default) 01 : port 1, 2 trunk-grouped 10 : port 1, 2, 3 trunk-grouped 11 : port 1, 2, 3, 4 trunk-grouped IL, PD Filter the packet with MAC destination address 01-80-c2-00-00-03~01-80-c2-00-00-0F 0 : Broadcast (Default) 1 : Filter IL, PD Enable 802.1Q TAG priority function of all ports 1:Enable; 0: Disable (Default) IL, PD Enable IP TOS/DS priority function of all ports 1: Enable; 0: Disable (Default) IL, PD Reserved for IC test.
47, 45
TRUNK_0_ON[1:0]
54
BPDU_BCST_OFF
59 61 63
TAG_PRI_ON IP_PRI_ON FAST_TEST_MODE
108,107,94,93, PORT_PRI_ON[5:0] IL, PD Enable port base high priority function of port 1~ port 6 92,91 1: Enable; 0: Disable (Default) 109,110 WRR_RATIO_SET[1:0] IL, PD The ratio of the packet number for the weighted round robin. The switch engine handles both priority queues based on the ratio of the packet number defined below. 00 : First in first out (Default) 01 : 2/1 10 : 4/1 11 : 8/1 When these bits are set to "00", the CoS priority will be void. 50, 26, 126 DELAY_SSSMII[2:0] IL, PD The delay time of SS-SMII transmit data delay_sssmii[0] : port 1~ port 8 delay_sssmii[1] : port 9~ port 16 delay_sssmii[2] : reserved 1: 4ns delay; 0: no delay(Default)
Note: 1. All the trapped pins are latched upon reset and are pulled down or pulled up by a 50K resistor inside the chip. 2. The designer can connect a 4.7K ohms resistor to set these pins to "1" or "0" to change the default state. 3. The content of an EEPROM will override the pin setting.
10/33 Copyright (c) 2003, IC Plus Corp.
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
4
4.1
Functional Description
Medium Access Control(MAC)
4.1.1 Data Rate Control The IP1718 LF implements a sophisticated data rate control mechanism, which is very useful for the bandwidth-limited network. By controlling both the ingress data rate and the egress data rate, the IP1718 LF provides a variety of the bandwidth configuration. By means of calculating the maximum TX/RX byte number in a time unit of the corresponding port, the IP1718 LF provides a precise bandwidth control mechanism. The formula for calculating the maximum byte during a time unit is: M.B.N= S.D.R* 512 Where M.B.N stands for the maximum byte number; S.D.R the specified data rate. The time unit is 10ms at 100 Mbps speed and 100ms at 10Mbps speed. The data rate for each port is specified in registers ranging from 03H to 12H and 1BH ~ 1CH. If the transmit/receive byte number reaches the specified M.B.N after the transmit/receive timer expires, the MAC will continue the operation until the whole data packet is transmitted/received and then wait until the next time unit starts. For example, if the value set to register 06H is 12H(18 in decimal) and the port 1 runs at 100Mbps speed, the maximum byte number allowed to transmit through port 1 is 9216 bytes(the result of 512*18) within 10ms( 1,000,000 bit time). 9216 bytes stands for 73,728 bit time. The flow control mechanism will be activated for the spare time. Thus the data rate can be limited to a specified value. 4.1.2 Flow Control The IP1718 LF embeds the flow control mechanism for both full duplex mode and half duplex mode. When the buffer reach a pre-defined level, the transmit MAC will generate the flow control pattern to prevent the buffer overflow. These flow control patterns are dependent on the duplex mode. The IP1718 LF transmit MAC generates the backpressure pattern in half duplex mode and the 802.3x pause packet in full duplex mode. When operating in half duplex mode, the IP1718 LF should comply with CSMA/CD standard. The transmit MAC will generate the jam pattern to inform the link partner that the receive buffer is not available when the buffer reaches a pre-defined level. The IP1718 LF supports the collision_based backpressure. When the collision_based backpressure is enabled, the transmit MAC of the IP1718 LF will generate the jam pattern only when the link partner is transmitting data and the buffer is not available. When detecting the collision on line, the link partner will back off the transmission and then wait until the back off time expires. The IP1718 LF uses 802.3x pause packet to accomplish the flow control for full duplex mode. When the buffer reach a pre-defined level, the transmit MAC generates a Xoff pause packet immediately or right after the current packet has been transmitted. When receiving a pause packet, the link partner will stop the transmission for a time period according to the pause value carried by the pause packet, preventing the internal buffer from overrun.
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
4.2 Switch Engine and Queue Management
4.2.1 Store & Forward Mechanism The IP1718 LF utilizes the "store & forward" method to handle the switch engine. Each data packet will not be forwarded to the destination port until the entire packet is received. The internal mechanism will check whether the packet is correct. The data packet will be forwarded to the destination port if the packet is correct; otherwise it will be discarded. Besides the erroneous packet and the 802.3x pause packet are not forwarded. The 802.1D Reserved Group packet with 01-80-c2-00-00-03 ~ 01-80-c2-00-00-0F MAC address can be optionally dropped by setting pin 54 or register 01H. 4.2.2 Address Learning and aging time The address learning function for each port can be either disabled or enabled by setting the corresponding bit in registers 31H and 32H. The overall MAC address capacity is 4096. The aging time can be programmed according to the system requirement, ranging from 30sec to 8400sec +-6.7%. The IP1718 LF provides two kinks of hash method to store the MAC address table. One is the direct mapping and the other is the CRC-12 algorithm. When the direct mapping method is selected, the IP1718 LF recognizes the least significant 12 bits of the source MAC address. When the CRC-12 algorithm is used, the IP1718 LF executes the following equation to decide the address of the MAC address table. CRC-12 equation: X^12+X^11+X^3+X^2+X+1 Some source MAC address will be excluded in MAC address table. These data packets are: Erroneous packet 802.3x pause packet 802.1D Reserved Group packet Multicast source MAC address 4.2.3 Class of Service The IP1718 LF implements two levels of priority queues, high priority and low priority. The priority for each data packet is based on one of the following schemes: 802.1Q VLAN tag, IP TOS/DS or physical port. Each incoming data packet can be mapped to either one priority. When no CoS function is enabled, the first-in first-out forwarding method is used. When the CoS for 802.1Q VLAN tag is enabled, the IP1718 LF will recognize 3 bits of precedence carried by the VLAN tag and map it to the specified priority. The data precedence 0 to 3 will be treated as low priority packet, and the packet with other values will be stored in high priority queue. Setting register 25H and 26H to "1" will enable the CoS function for the corresponding port. The LSB of both registers controls the lowest port ID for that group. For example, the bit 0 of register 25H corresponds to port 1. The IP1718 LF provides the IP layer CoS function by recognizing the DSCP(Differentiated Service Code Point) Octet and mapping it to the specified priority. For IPv4 packet, DSCP is embedded in the TOS(type of Service) Octet. For a IPv6 data packet, the Traffic Class Octet can be used to differentiate the Class of Service. When this function is enabled, the IP1718 LF will automatically recognize the IP version and capture the either the TOS field(IPv4) or Traffic Class(IPv6). The following tables show the location of DSCP in a packet. Destination MAC Source MAC Address(6 bytes) Address(6 bytes) 0800H IP version = 0100b(4 bits)
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IHL(4 bits)
TOS(8 bits). IP1718 LF maps TOS[5:0] to 2 levels of
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
priority. Table 4.1 IPv4 Data Format Destination MAC Source MAC Address(6 bytes) Address(6 bytes) 0800H IP version = 0110b(4 bits) Traffic Class(8 bits). IP1718 LF maps TC[5:0] to 2 levels of priority.
Table 4.2 IPv6 Data Format
802.1Q VLAN tag Precedence IPv6 Traffic Class Field & IPv4 TOS
High Priority 3'b100 ~ 3'b111 6'b101110; 6'b001010; 6'b010010; 6'b011010; 6'b100010; 6'b11x000
Low Priority 3'b000 ~ 3'b011 Other values
Table 4.3 Forwarding Priority for IP DS and 802.1Q VLAN tag The IP TOS/DS priority configuration can be set through enabling the corresponding register, ranging from 27H to 28H. The port based priority only concerns the physical port location in a switch. By enabling the CoS function of the corresponding bit in registers 23H and 24H, the IP1718 LF can set each physical port to a "high" priority. Please note that for those three CoS functions, the LSB (Least Significant Bit) of the registers corresponds to the low physical port number for that group. A data packet dropping mechanism is implemented to prevent the buffer from overrun. Once the packet buffer reach a specified level, the data packet assigned to the low priority will be dropped to reserve the buffer space for the high priority data packet. When multiple CoS schemes are enabled, the data packet is treated as the high priority as long as any one of three CoS schemes is mapped to "high". Take the following example for detailed explanation. If port 3 is set as a low priority port and it receives a data packet which embeds VLAN tag with high priority and IP DS field with low priority, this data packet will be forwarded in a high priority. In the other word, the priority of a data packet would be set to high if any of three CoS schemes is interpreted as the high priority. 4.2.4 Port_based VLAN The IP1718 LF provides various port_based VLAN configurations. The overall number of VALN groups that the IP1718 LF can support is 18. The IP1718 LF implements two registers to describe the routing table for each port. Thus the total number of registers which defines the port_based VLAN is 52. Take the following example for the detailed description. The data incoming from port 1 will be forwarded to the corresponding port defined in register 34H and 35H. Similarly, the forwarding rule for the data incoming from port 2 will refer to the register 36H and 37H. Note: The port ID is counted from 1 to 18.
13/33 Copyright (c) 2003, IC Plus Corp. January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
4.2.5 Trunk Channel Supporting up to 3 trunk channels, the IP1718 LF provides a versatile configurations that fit many applications. Each trunk channel may comprise 2 to 4 ports. The traffic of the destination port passing through the trunk channel is defined by the registers 68H to 6AH. The hash algorithm from which the IP1718 LF derives the trunk ID is specified by registers 2FH. The result calculated by the hash algorithm is mapped to the trunk ID. A physical port can forward the trunk traffic only when the trunk ID decided by hash algorithm matches the setting of the Trunk Configuration register. The following table describes the traffic distribution rule. The Behavior for Each Port in a Trunk Result of the Hash Algorithm 2'b00 Trunk Channel Configuration 4'bXXX1 4'bXXX0 2'b01 4'bXX1X 4'bXX0X 2'b10 4'bX1XX 4'bX0XX 2'b11 4'b1XXXX 4'b0XXXX Behavior of the Member of Trunk Forward the data through the first port of this group Do not forward the data through the first port of this group Forward the data through the second port of this group Do not forward the data through the second port of this group Forward the data through the third port of this group Do not forward the data through the third 7 port of this group Forward the data through the fourth port of this group Do not forward the data through the fourth port of this group
There are four ports for each trunk and each port can be configured to fit the trunk traffic as depicted above. 4.2.6 Port Mirroring There are some circumstances that the network administrator requires to monitor the network status. The port mirroring function can help the network administrator diagnose the network. A port mirroring function can be accomplished by assigning a monitored port(source port) and a snooping port (destination port). The IP1718 LF supports three kinks of mirroring methods: the ingress, the egress and ingress plus egress. This function can be enabled by programming the corresponding bit in registers 6BH to 6DH. Registers 6BH and 6CH defined the port which will be monitored(mirroring source). The register 6DH specifies the port which will snoop( mirroring destination) and the mirroring method. 4.2.7 Queue Management The IP1718 LF supports three kinds of priority management: The first in first out, the strict priority and the weighted-round-robin.
14/33 Copyright (c) 2003, IC Plus Corp. January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
The first in first out method will override the CoS setting and is not recommended when the CoS function is enabled. When the strict priority is enabled, the data packets stored in low priority queue will not be sent out until all data packets in high priority queue are sent out. When the weighted round robin function is enabled, the IP1718 LF will send the data packet in an order switching between high priority queue and low priority queue with ratio defined by pin 109,110 setting (without EEPROM) or Register 2CH(with EEPROM/CPU) 4.2.8 Broadcast Storm Control To prevent the broadcast storm, the IP1718 LF implement a broadcast storm control mechanism. When this function is enabled, the IP1718 LF will monitor the number of the broadcast packet and take the proper action to prevent the broadcast packet from reaching the pre-defined buffer level. The behavior of the broadcast packet is dependent on the operating mode of the IP1718 LF. Drop the data when the flow control is disabled
4.2.9 Handling the Higher Layer Protocol The IP1718 LF can handle two categories of data packet, the configuration related and the TCP/IP related. The configuration-related protocol concerns the network configuration such as, the VLAN group, the link aggregation and the spanning tree. Unlike the configuration-related protocol, the TCP/IP related data has nothing to do with the network. Four forwarding schemes can be selected to handle the protocol mentioned above, dropping the packet, sending to a specified port(commonly connected to a CPU), sending to a group of ports and broadcasting to all ports. The protocol handling scheme is programmed by writing the corresponding bit in register 02H. 4.2.10 Port Security In some cases, it is required to disable the address learning mechanism and specify the MAC address. This function is useful for the application which will prevent the unauthorized user from intruding the network. The typical application is the Ethernet to the Home(ETTH). Programming the registers 31H and 32H will enable/disable the address learning function. The LSB of the register 31H corresponds port 1. The register 33H handles the forwarding rule. A data packet will be either forwarded or dropped depending on the setting of this register.
15/33 Copyright (c) 2003, IC Plus Corp.
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
5
5.1
System Operation
Reset and EEPROM Download Procedure
The reset input should be kept at "0" for more than 1.6 microsecond after power up. After detecting the rising edge of reset input, the IP1718 LF will start downloading the content of EEPROM(acting like an EEPROM master). The internal register address of the IP1718 LF should comply with the address of EEPROM. Being an EEPROM master, the IP1718 LF will download the content of EEPROM with EEPROM ID "1726H". The mapping relationship between the IP1718 LF registers and the EEPROM address are depicted as the following table. EEPROM address 00H 01H 02H 03H 04H 05H ****** ****** FCH FDH EEPROM content 17H 26H Expected value Expected value Expected value Expected value ****** ****** Expected value Expected value IP1718 LF Register XX XX 01H[15:8] 01H[7:0] 02H[15:8] 02H[7:0] ****** ****** 7EH[15:8] 7EH[8:0]
Note: 1. The EEPROM ID should be set to "3'b000"; i.e. A2=0; A1=0; A0=0 2. The IP1718 LF download the content of the EEPROM ranging from address 00H to FDH; i.e. the register beyond this range is not recognized by the IP1718 LF. 3. The ID for IP1718 LF recognition should be set at address 00H and address 01H as stated in the table.
5.2
Polling/Writing the PHY
The IP1718 LF periodically, around 2.8ms for each access cycle, read the status of the PHY through MDC, MDIO management signals. The PHY registers that will be read/write are 0, 1, 4 and 5. After reading the PHY status, the IP1718 LF will reconfigure the internal MAC to meet the operating mode of the PHY. The relationship between the port ID and the PHY ID is shown below. IP1718 LF Port ID PHY ID Comment Port 1 to Port 24 address 8 to address 31 The smallest ID of the IP1718 corresponds to the smallest PHY ID. LF Port 17 address 4 Port 18 address 5
Table 5.1 The Relationship between PHY ID and the IP1718 LF Port ID
16/33 Copyright (c) 2003, IC Plus Corp.
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
The IP1718 LF can be enforced to run at a specified mode without referring to the PHY status. When enforced, the IP1718 LF will write the forced mode to the corresponding PHY through MDC/MDIO and poll the link status of PHY. Care should be taken that the operating mode in both MAC side and PHY side should be consistent. By programming the register 80H and 81H, the user can easily set the PHY register to a specified value. Since the MDC runs at 2.5 Mhz clock speed, the CPU should check whether the current command has been completed or not before issuing the next command. Bit 13 in the register 80H indicates the progress of the read/write operation.
5.3
Programming the Internal Registers
There is no need to program the register of the IP1718 LF for the generic application. However it's probably necessary to program the internal register to fit some special applications. The interface between the IP1718 LF and the CPU is a serial bus which comprises a clock and a I/O signal. Like the access cycle of the serial management interface, the serial interface comprises the device ID, the read/write command, the address and the data. The access cycle is depicted as below.
Driven by the CPU
"1" "0" "1" "1" "0"
"0" "0" A7
Driven by the IP1726
A4 A3 A2 A1 A0
A6
A5
"Z"
"0" D15
D14 D13
........ .
D0
SCPUIO SCPUC
Fig. 5.1 The CPU read data from the IP1718 LF
Driven by the CPU
"1" "0" "1" "0" "1"
"0"
"0"
A7
A6
A5
A4
A3
A2
A1
A0
"1"
"0" D15 D14 D13
........ .
D0
SCPUIO SCPUC
Fig. 5.2 The CPU write data to the IP1718 LF
The access cycle is much like the access cycle of MDC, MDIO. Care should be taken that the switch ID is 2-bit wide rather than 5-bit wide.
5.4
SS-SMII
The transmitter of the MAC transfers the transmit data to the PHY at the rising edge of TXCLK and the TXSYNC indicates the start of the 10-bit frame. By recognizing the high pulse of the TXSYNC, the PHY can capture the correct transmit data stream. The PHY transfers the receive data to the IP1718 LF in a similar way. The difference is that the signal direction is reverse. Accompanied by the high pulse of TXSYNC, the TXEN status is present on the TXDATA pin and then the TX-ER status and finally 8-bit data. For the RX part of SS-SMII, the CRS(Carrier Sense) status is present
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IP1718 LF
Preliminary Data Sheet
on the RXDATA during the high pulse of RXSYNC. The RX_DV(receive data valid) status follows CRS and finally the 8-bit data. For a given PHY port, the SS-SMII consists of six signals. RXDATA-one bit data for receiver TXDATA- one bit data for transmitter TXSYNC- This signal is driven by MAC. RXSYNC- This signal is driven by PHY. TXCLK- This signal is driven by MAC RXCLK- This signal is driven by PHY.
TXCLK
TX_SYNC
TX_D[0]
TXER
TXEN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TXER
Transmit SS-SMII
RXCLK
RX_SYNC
RX_D[0]
CRS
RXDV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
CRS
Receive SS-SMII
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
6 Register Map
R = Read ; W = Write ; R/W = Read/Write Register Register Description Address 01H Half duplex control Bit [0]: Drops the packet that encounters 16 successive collisions. 1: Drop; 0: Forward Bit [1]: Collision back off. 1: Disable; 0: Enable Bit [2]: Reserved and should be set to "0". Bit [3]: Broadcast BPDU packet. 1: Broadcast; 0: Drop Bit [4]: Reserved and should be set to "0". Bit [15]~ Bit 5: Not used. 02H Attribute R/W Default value 5'h0A
R/W Network configuration packet capture: Bit [0]: Spanning tree. 1: Capture & forward to the CPU port. 0: Drop. Bit[1]: In-band management packet(Destinatopn MAC Address =This Switch MAC Address) 1: Capture & forward to the CPU port. 0: Drop Note: If this bit is set to "1", the ARP will be sent to CPU port too. Bit[2]: LACP 1: Only forward to the CPU port when register1 bit[3]= 0. Braodcast to other ports when register1 bit[3]=1 0: Drop Bit[3]: GVRP 1: Capture & forward to the CPU port only . 0: Broadcast IP packet capture Bit[5:4] : ICMP Bit[7:6] : IGMP Bit[9:8] : TCP Bit[11:10] : UDP Bit[13:12] : OSPF Bit[15:14] : Others 00 : Send to port 1 ~ port 16 only 01 : Send to port 18(CPU) and port 1 ~ port 16 10 : Send to port 18(CPU) only Note: 1. When the packet capture function is enabled, port 18 should be set to as CPU port. 2. If only one CPU port is required, it's recommedded to set port 18 as the CPU port.
16'h0000
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Register Address 03H Register Description Attribute Default value 16'hffff
Egress/Ingress data rate control. R/W Bit[7:0]: Egress data rate control. Bit[15:8]: Ingress data rate control. The maximum ingress/egress byte number in one time unit is. Bit[15:8] * 512 for Ingress Bit[7:0] * 512 for Egress. The one time unit is 10ms for 100Mbps seed and 100ms for 10Mbps speed.
04H ~ 12H 04H ~ 12H: Egress/Ingress data rate control for port 2 to port 16. R/W 04H register corresponds to port 2. 1BH~ 1CH 1BH ~ 1CH: Egress/Ingress data rate control for port 17 and port 18. 1BH register corresponds to port 17. The definition is the same as that of the register 03H. 1DH Port receive function. R/W 1: Enable; 0: Disable. Bit 0 corresponds to port 1. Bit 15 corresponds to port 16. 1E Port receive function. R/W Bit[9:8] 1: Enable; 0: Disable. Bit 8 and bit 9 correspond to port 17 and port 18 respectively. Other bits are reserved. MAC reset for port 1 to port 16. R/W 0: Activate reset; 1: normal operation. Bit 0 corresponds to port 1. Bit 15 corresponds to port 16. MAC reset for port 17 and port 18. R/W Bit[9:8] 0: Activate reset; 1: normal operation. Bit 8 and bit 9 correspond to port 17 and port 18 respectively. Other bits are reserved. MAC filters the data frames for port16~pot1, 1 bit per port 0: only control frames are forwarded 1: all good frames are forwarded MAC filters the data frames for port 17 and port 18, 1 bit per port bit[9:8] : 0: only control frames are forwarded 1: all good frames are forwarded Other bits are reserved Port base priority enable for port16~pot1, 1 bit per port bit[15:0] : 0: This port is set to normal priority 1: This port is set to high priority Port base priority enable for port 17 and port 18, 1 bit per port bit[9:8] : 0: This port is set to normal priority 1: This port is set to high priority Other bits are reserved VLAN Tag based priority enable for port16~pot1, 1 bit per port bit[15:0] : 0: disable 1: enable R/W
16'hffff
16'Hffff
10'h3ff
1FH
16'hffff
20H
10'h3ff
21H
16'hffff
22H
R/W
10'h3ff
23H
R/W
16'h0
24H
R/W
10'h0
25H
R/W
16'h0
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Register Address 26H Register Description Attribute Default value 10'h0
27H
VLAN Tag based priority enable for pot17 and port 18, 1 bit per port R/W bit[9:8] : 0: disable 1: enable Other bits are reserved. IP DS based priority enable for port16~pot1, 1 bit per port R/W bit[15:0] : 0: disable 1: enable IP DS based priority enable for port 17 and pott 18, 1 bit per port bit[9:8] : 0: disable 1: enable Other bits are reserved. Switch MAC address[15:0] Switch MAC address[31:16] Switch MAC address[47:32] R/W
16'h0
28H
10'h0
29H 2AH 2BH 2CH
R/W R/W R/W
16'h0 16'h0 16'h0 8'd0
R/W Out queue schedule mode / weight selection Bit[1:0] : Schedule mode 2'b00: First in First out 2'b01: Strict Priority. The IP1718 LF will always forward all packets with high priority until the packet in the high priority queue is empty. 2'b10 : WRR. Weighted-and-round-robin scheme.The packet number in both priority queues is based on the defined ratio. 2'b11 : undefined Bit[4:2] : Low priority queue weight number when the WRR mode is selected Bit[7:5] : High priority queue weight number when the WRR mode is selected. Note: When Bit[4:2] and Bit[7:5] are set to "000", the weight number will be interpreted as "8".
2DH 2EH
Reserved for test. Do not access to this register. Reserved for test. Do not access to this register.
R/W R/W
9'd475 9'd500
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Register Address 2FH Register Description Attribute Default value 8'h0
bit[0] : Hash algorithm selection R/W 0 : CRC mapping 1 : Direct mapping bit[1] : Address table aging function disable 0 : aging function enabled 1 : aging function disabled bit[3:2] : Trunk ID hash algorithm selection 2'b00 : Port ID(the least significant 2 bits of the result of port ID +1); Note: The port ID is counted from 1 to 18. 2'b01 : SA(the least significant 2 bits of the source MAC address) 2'b10 : DA(address bit 16 is mapped to trunk ID[1] and address bit 0 is mapped to trunk ID[0] ); 2'b11 : SA XOR DA(the result of the XOR operation described above) bit[4] : Broadcast Strom Control enable 0 : broadcast storm control disabled 1 : broadcast storm control enabled bit[5] : Auto turn on/off flow control when priority queue enable 0 : normal flow control 1 : auto turn on/off flow control bit[6] : Broadcast frames egress is blocked for port 17 0 : Broadcast frames send to port 17 1 : Broadcast frames do not send to port 17 bit[7] : Broadcast frames egress is blocked for port 18 bit[7:0] : Aging timer The aging time is about : (aging_timer + 1) x 30.7 +-6.7% sec. bit[14:8] : Broadcast storm control threshold The broadcast frame number allow in one time unit The time period is 1ms for 100M speed The time period is 10ms for 10M speed Enable Source MAC address learning function for port16~1 bit[15:0] : 0: disable learning 1: enable learning Enable Source MAC address learning function for port 18~ port 17 bit[9:8] : 0: disable learning 1: enable learning R/W
30H
8'd9
8h'7f R/W 16'hffff
31H
32H
R/W
10'h3ff
33H
Security configuration R/W bit[0] : Drop the unknown SA frame going to port 18 0 : forward 1 : Drop bit[1] : forward unknown Source MAC address frame when the address learning function is disabled 0 : drop the frame with unknown source MAC addreess 1 : forward the frame with unknown source MAC addreess
2'b10
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Register Address 34H Register Description Attribute Default value 16'hffff
VLAN group setting for port 1 (p16~p01) R/W The bit 15 corresponds to port 16 and the LSB corresponds to port 1. 0: The data incoming from port 1 is NOT allowed to be forwarded to the corresponding port. 1: The data incoming from port 1 is allowed to be forwarded to the corresponding port. VLAN group setting for port 1 (p18~p17) R/W The bit 9 corresponds to port 18 and bit 8 corresponds to port 17. Other bits are reserved. 0: The data incoming from port 1 is NOT allowed to be forwarded to the corresponding port. 1: The data incoming from port 1 is allowed to be forwarded to the corresponding port. The registers within this range are used to define the VLAN group R/W setting for port 2 to port 16. Like the statement of registers 34H and 35H, two registers comprise the definition of the forwarding rule for a port. Reserved The registers within this range are used to define the VLAN group R/W setting for port 17 and port 18.
35H
10'h3ff
36H~ 53H
16'hffff &10'h3ff
54H~63H 64H~67H
16'hffff &10'h3ff
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Register Address 68H Register Description Attribute Default value 16'h0000
R/W Trunk group 0 (p4, p3, p2, p1) setting port 1 ~ port 4 are the same trunk group and can be any combination to form a trunk. The trunk ID described below is derived by the algorithm defined in register 2FH. bit[3:0] : trunk configuration for port 01 4'b0000 : the trunk is disabled. 4'bxxx1 : pass the frame with trunk ID = 0 4'bxx1x : pass the frame with trunk ID = 1 4'bx1xx : pass the frame with trunk ID = 2 4'b1xxx : pass the frame with trunk ID = 3 bit[7:4] : trunk configuration for port 02 bit[11:8] : trunk configuration for port 03 bit[15:12] : trunk configuration for port 04 Note : In a trunk group, the configuration should be ORed to 4'b1111 and no more than one port has the same configuration bit. Example 1: bit[3:0] = 4'b1100, bit[7:4] = 4'b0010, bit[11:8]=4'b0001, bit[15:12]=4'b0000. This configuration stands for the following forwarding rule. Forwarding to port 1 of this group when the hash result defined register 21H is 3 or 2. Forwarding to port 2 of this group when the hash result defined register 21H is 1. Forwarding to port 3 of this group when the hash result defined register 21H is 0. Port 4 is not allowed to forward the data since bit[15:12] is set 4'b0000.
in in in to
Example 2: Bit[3:0]=4'b1100, bit[15:12]=4'b1000 is not allowed. When the hash result is 3, the switch can not decide to forward the packet through either port 1 or port 4. 69H Trunk group 1 (p8, p7, p6, p5) setting R/W port 5 ~ port 8 are the same trunk group and can be any combination to form a trunk bit[3:0] : trunk configuration for port 05 bit[7:4] : trunk configuration for port 06 bit[11:8] : trunk configuration for port 07 bit[15:12] : trunk configuration for port 08 Trunk group 2 (port 17, port 18) setting port 17 ~port 18 are the same trunk group bit[3:0] : trunk configuration for port 17 bit[7:4] : trunk configuration for port 18 R/W 16'd0
6AH
8'h00
24/33 Copyright (c) 2003, IC Plus Corp.
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Register Address 6BH Register Description Port Mirroring Configuration 0 bit[15:0] : p16~p01 monitored port (source port) 0 : this port is not monitored 1 : this port is monitored The LSB corresponds to port 1. Port Mirroring Configuration 1 bit[9:8] : p18~p17 monitored port (source port) 0 : this port is not monitored 1 : this port is monitored The bit 8 corresponds to port 17. Port Mirroring Configuration 2 bit[4:0] : the snooping port(destination) 5'h0: port 1 .... .... 5'h15: port 16 5'h19: port 17 5'h1A: port 18 bit[6:5] : the port snooping scheme 00 : disabled 01 : egress 10 : ingress 11 : egress/ingress (Reserved) CPU read/write MAC address table Configuration bit[11:0] : the 4K SRAM address for MAC address table bit[12] : read/write configuration 0 : read 1 : write bit[13] : 70H data indicator 0 : 70H is the data read from the table 1 : 70H is the data to be written to table bit[14] : read/write enable 0 : No action 1 : read/write table bit[15] : command complete CPU read/write table Data [15:0] Store the data read from table for read command Store the data to be written to table for write command CPU read/write table Data [31:16] Store the data read from table for read command Store the data to be written to table for write command CPU read/write table Data [45:32] Store the data read from table for read command Store the data to be written to table for write command Auto negotiation for port16~pot1, 1 bit per port bit[15:0] : 0: auto negotiation disabled 1: auto negotiation enabled R/W 16'h0000 Attribute R/W Default value 16'h0000
6CH
R/W
10'h000
6DH
R/W
7'd0
6EH 6FH
70H
R/W
16'd0
71H
R/W
16'd0
72H
R/W
14'd0
73H
R/W
16'hffff
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Register Address 74H Register Description Attribute Default value 10'h3ff
Auto negotiation for port18~pot17, 1 bit per port R/W bit[9:8] : 0: auto negotiation disable; 1: auto negotiation enable Other bits are reserved. Speed setting for port16~pot1, 1 bit per port bit[15:0] : 0: 10Mb 1: 100Mb The LSB corresponds to port 1. Speed setting for port18~pot17, 1 bit per port bit[9:8] : 0: 10Mb; 1: 100Mb The bit 8 corresponds to port 17. Other bits are reserved. Duplex setting for port16~pot1, 1 bit per port bit[15:0] : 0: Half duplex; 1: Full duplex The LSB corresponds to port 1. Duplex setting for port18~pot17, 1 bit per port bit[9:8] : 0: Half duplex; 1: Full duplex The bit 8 corresponds to port 17. Other bits are reserved. Pause setting for port16~pot1, 1 bit per port bit[15:0] : 0: disabled 1: enabled The LSB corresponds to port 1. Pause setting for port18~pot17, 1 bit per port bit[9:8] : 0: disabled; 1: enabled The bit8 corresponds to port 17. Other bits are reserved. Backpressure setting for port16~pot1, 1 bit per port bit[15:0] : 0: disabled; 1: enabled The LSB corresponds to port 1. Backpressure setting for port18~pot17, 1 bit per port bit[9:8] : 0: disable; 1: enable The bit8 corresponds to port 17. Other bits are reserved. Transmit enable for port16~pot1, 1 bit per port bit[15:0] : 0: Tx. disabled 1: Tx. Enabled The LSB corresponds to port 1. Transmit enable for port18~pot17, 1 bit per port bit[9:8] : 0: Tx. Disabled; 1: Tx. Enabled The bit8 corresponds to port 17. Other bits are reserved. R/W
75H
16'hffff
76H
R/W
10'h3ff
77H
R/W
16'hffff
78H
R/W
10'h3ff
79H
R/W
16'hffff
7AH
R/W
10'h3ff
7BH
R/W
16'hffff
7CH
R/W
10'h3ff
7DH
R/W
16'hffff
7EH
R/W
10'h3ff
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Register Address 80H Register Description CPU read/write PHY register command bit[4:0] : the PHY address bit[9:5] : the MII register address bit[12:10] : (Reserved) bit[13] : 1: the read/write command has been completed 0: not yet bit[14] : 0: read operation, 1: write operation bit[15] : the read/write command trigger 0: IDLE or command complete 1: Start command Attribute R/W Default value 16'd0
81H
CPU read/ write PHY register data R/W bit[15:0] : the data to be written into PHY register for write command. The last data read from PHY register read command. Port status of port4~pot1, 4 bit per port R bit[3:0] : {flow_ctrl, duplex, speed, link}. Bit[15:4] indicates the operating mode for port4 to port2. Port status for port5 to port16. Link status port18~pot17, 4 bit per port bit[7:0] : {flow_ctrl, duplex, speed, link} Bit0~bit4 stands fot the operating mode for port 17. bit[15] : share memory over-flow indication bit[14] : share memory under-flow indiaction bit[10:0] : share memory current page count R R
16'd0
82H
16'd0
83H~85H 88H
16'd0 16'd0
90H
R
16'hxx
91H 92H A0H
Reserved for test Reserved for test bit[0] : Interrupt enable for completing CPU r/w SMI command 1: Enable interrupt indication; 0: No interrupt bit[4] : Status of the CPU r/w SMI command 1: Command completed; 0: Command processing
Reserved Reserved R/W
16'hxx 16'hxx 5'h00
A1 A2H
Do not access to this register.
Reserved
16'h000f 1'b0
bit[0] : Software reset. Writing a "1" to this bit will reset the IP1718 W LF. This bit is self-cleared to "0".
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January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
7
7.1
Electrical Characteristics
Absolute Maximum Rating
Permanent device damage may occur if Absolute Maximum Ratings are applied. Functional operation should be restricted to the conditions as specified in the following section. Exposure to the Absolute Maximum Conditions for extended periods may affect device reliability. PARAMETER Supply Voltage Input Voltage Output Voltage Storage Temperature Operation Temperature I/O Core VDDI/O VDDCore VI VO TSTG TOPT SYMBOL - 0.5 - 0.5 - 0.5 - 0.5 -65 0 MIN. MAX. +3.6V +1.9V VDDI/O VDDI/O +150 +70 UNIT V V V V C C
Note: The maximum ratings are the limit value that must never be exceeded even for short time.
7.2
AC Characteristics
SS-SMII Transmit Timing Symbol TTx_Clk Description Transmit clock cycle time Tx_Clk rising edge to TX_Sync output delay Tx_Clk rising edge to TXD output delay Min. 1.0 1.0 Typ. 8 Max. 5.0 5.0 Unit ns ns ns
TTSync_D TTData_D
TTx_Clk
Tx_Clk TxSync TxData
TTSync_D
TTData_D
SS-SMII Transmit
SS-SMII Receive Timing Symbol TRx_Clk TRSync_SU TRdata_H TRdata_SU TRData_H Description Receive clock cycle time Rx_Sync Set up time Rx_Sync Hold time RxData Set up time RxData Hold time
28/33 Copyright (c) 2003, IC Plus Corp.
Min. 2.0 1.0 2.0 1.0
Typ. 8 -
Max. -
Unit ns ns ns ns ns
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
TRx_Clk
Rx_Clk RxSync RxData
TRSync_H
TRSync_SU
TRData_SU
TRData_H
SS-SMII Receive
PHY Management (MDIO) Timing Symbol Tch Tcl Tcm TMD_SU TMD_H TMD_D Description MDCK High Time MDCK Low Time MDCK cycle time MDIO set up time MDIO hold time MDIO output delay time
MDClk Tcl Tcm MDIO (Input) TMD_SU Tch TMD_H
Min. 10 10 200
Typ. 200 200 400 -
Max. 210
Unit ns ns ns ns ns ns
MDIO Input Cycle
MDClk
TMD_D MDIO (Output)
MDIO Output Cicle
29/33 Copyright (c) 2003, IC Plus Corp.
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
CPU Serial Bus Timing Symbol TS_C TSIO_SU TSIO_H TSIO_D Description SCPUC cycle time Serial I/O set up time Serial I/O hold time Serial I/O output delay time
SCPUC
Min. 400 10 10
Typ. -
Max.
20
Unit ns ns ns ns
TS_C TSIO_SU TSIO_H
SCPUIO (Input)
Serial I/O Input Cycle
SCPUC
TSIO_D SCPUIO (Output)
Serial I/O Output Cycle
MII Transmit Timing Symbol TTxClk TTxClk TTxClk_SU TTxClk_H Description Transmit clock period 100Mbps MII Transmit clock period 10Mbps MII TXEN, TXD to MII_TXCLK setup time TXEN, TXD to MII_TXCLK hold time
T T xC lk
Min. 2 0.5
Typ. 40 400 -
Max. -
Unit ns ns ns ns
M II_T X C LK T T xC lk_H T X E N , T X D [3:0 ] T T xC lk _S U
30/33 Copyright (c) 2003, IC Plus Corp.
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
MII Receive Timing Symbol TRxClk TRxClk TRxClk_D Description Receive clock period 100Mbps MII Receive clock period 10Mbps MII MII_RXCLK falling edge to RXDV, RXD Min. 1 Typ. 40 400 Max. 4 Unit ns ns ns
TRxClk
MII_RXCLK
TRxClk_H
RXDV, RXD[3:0]
7.3
DC Characteristics
SYMBOL VOL VOH IOL IOH MIN. 1.7V for 1.8V I/O supply voltage; 3V for 3.3V I/O supply voltage; TYP. MAX. 0.4 UNIT V V mA
PARAMETER Output low voltage Output high voltage Low level output current High level output current VDD33 supply current VDD18 supply current VDDPLL supply current VDD33 supply voltage VDD18 supply voltage VDDPLL supply voltage SS-SMII Input Low to High treshold point(3.3V operation) SS-SMII Input High to Low treshold point(3.3V operation) Pull-down resistor
1.8 or 3.3 1.8 1.8 VT+ 1.66 1.75 1.79
V V V V
VT-
0.93
1.01
1.06
V
RPD
51
127
K
Jc Ja
31/33 Copyright (c) 2003, IC Plus Corp.
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
8 Order Information
Part No. IP1718 IP1718 LF Package 128-PIN PQFP 128-PIN PQFP Notice Lead free
32/33 Copyright (c) 2003, IC Plus Corp.
January 27, 2005 IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
9 Package Detail
HD D
128 103
128 PQFP Outline Dimensions
1
102
38
65
39
64
e
b GAGE PLANE A2
c
HE
E
Symbol A1 A2 b c HD D HE E e L L1 y
Dimensions In Inches Min. Nom. Max. 0.010 0.014 0.018 0.107 0.112 0.117 0.007 0.009 0.011 0.004 0.006 0.008 0.669 0.677 0.685 0.547 0.551 0.555 0.906 0.913 0.921 0.783 0.787 0.791 0.020 0.025 0.035 0.041 0.063 0.004 0 12
Dimensions In mm Min. Nom. Max. 0.25 0.35 0.45 2.73 2.85 2.97 0.17 0.22 0.27 0.09 0.15 0.20 17.00 17.20 17.40 13.90 14.00 14.10 23.00 23.20 23.40 19.90 20.00 20.10 0.50 0.65 0.88 1.03 1.60 0.10 0 12
D
L1
y
A1
L
Note: 1. Dimension D & E do not include mold protrusion. 2. Dimension B does not include dambar protrusion. Total in excess of the B dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
IC Plus Corp.
Headquarters 10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2, Hsin-Chu City, Taiwan 300, R.O.C. TEL : 886-3-575-0275 FAX : 886-3-575-0475 Website: www.icplus.com.tw Sales Office 4F, No. 106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. TEL : 886-2-2696-1669 FAX : 886-2-2696-2220
33/33 Copyright (c) 2003, IC Plus Corp.
January 27, 2005 IP1718 LF-DS-R05

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